The authors detail their development of a constraints-aware simulated annealing (CA-SA) algorithm, which they claim outperforms both machine-learning models and other SA-based algorithms in solving floorplanning problems. They also discuss their creation of open datasets of sample floorplans to serve as modern benchmarks for validating new chip-design tools. They conclude by predicting that hybrid algorithms, which combine AI with other methods, will be the most successful in the future of chip design.
Key takeaways:
- The complexity of modern chip design has outgrown the capabilities of current software tools, leading to a growing interest in using machine learning to speed up the process. However, machine-learning algorithms often fall short when dealing with multiple constraints.
- The authors developed a tool based on non-AI methods like classical search, which proved more successful than AI-based solutions for a design task known as floorplanning. They believe hybrid approaches combining AI and traditional techniques will be the most fruitful path forward.
- The authors created a new twist on a search technique called simulated annealing (SA), which they call constraints-aware SA (CA-SA). This variation employs two algorithmic modules, one for optimizing area and wirelength and another for fixing random constraint violations. This approach led to the development of an open-source floorplanning tool called Parsac.
- The authors also created open datasets of sample floorplans, called FloorSet-Lite and FloorSet-Prime, to serve as new benchmarks in the field. These datasets, which capture the full breadth and complexity of contemporary SoC floorplans, are available on GitHub.