The new UCIe IP subsystem aims to revolutionize connectivity by delivering a bandwidth density of over 20 Tbps/mm with ultra-low power and latency. It facilitates a range of chiplet connectivity scenarios, including linking compute chiplets and connecting compute to I/O chiplets using UCIe interfaces with PCIe, CXL, or Ethernet. This development supports low-power, high-speed solutions in data centers and AI/ML systems. Alphawave Semi's achievement in this area reaffirms its position as a leader in high-performance chiplet connectivity solutions, with a full suite of silicon-proven connectivity IP subsystems tailored for hyperscaler and data-infrastructure markets.
Key takeaways:
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- Alphawave Semi introduces the industry's first 64 Gbps Universal Chiplet Interconnect Express (UCIe™) Die-to-Die IP Subsystem, setting a new standard for ultra-high-performance chiplet interconnect data rates.
- The Gen3 64 Gbps IP Subsystem is available in TSMC’s 3nm Technology and supports both Standard and Advanced packaging, building on the success of previous generations.
- The UCIe IP is highly configurable, supporting multiple protocols and designed for high-performance connectivity in High-Performance Computing (HPC), Data Centers, and AI applications.
- Alphawave Semi's advancements in UCIe technology aim to revolutionize connectivity with a focus on low power, low latency, and high bandwidth solutions for critical AI and data infrastructure needs.