Axelera AI, with €61.6 million in funding, is advancing its Titania chiplet for server-grade workloads, building on its current AI ASICs design. Codasip plans to expand its RISC-V CPU cores for high-performance applications, while little is known about Openchip's vector accelerator. The initiative reflects a broader global interest in RISC-V as a foundation for technological independence, with countries like India and China also pursuing RISC-V-based designs. Despite its open nature, there have been calls in the US to restrict China's access to RISC-V technology.
Key takeaways:
- A group of 38 tech players in Europe has launched the Digital Autonomy with RISC-V in Europe (DARE) project to develop processor units for supercomputers and high-performance machines.
- The DARE project is supported by the EuroHPC Joint Undertaking and coordinated by the Barcelona Supercomputing Center, with a goal to create three RISC-V chiplets in three years.
- Axelera AI, part of the DARE project, is developing a datacenter-class RISC-V chip called Titania, designed for server-grade workloads, and has received significant funding from EuroHPC.
- RISC-V is gaining global traction as a royalty-free ISA, with countries like India and China pursuing domestic chip designs based on it, while the US considers restricting China's access to the technology.